iverilog 12.0-2
| Architecture: | x86_64 |
|---|---|
| Repository: | Extra |
| Description: | Icarus Verilog compiler and simulation tool |
| Upstream URL: | https://github.com/steveicarus/iverilog |
| License(s): | GPL |
| Maintainers: |
Filipe Laíns Frederik Schwan |
| Package Size: | 2.0 MB |
| Installed Size: | 6.1 MB |
| Last Packager: | Frederik Schwan |
| Build Date: | 2024-05-01 15:29 UTC |
| Signed By: | Frederik Schwan |
| Signature Date: | 2024-05-01 15:30 UTC |
| Last Updated: | 2024-05-01 15:31 UTC |
Required By (6)
- fusesoc (optional)
- fusesoc (staging) (optional)
- python-edalize (check)
- python-edalize (staging) (check)
- yosys (check)
- yosys (staging) (check)